This invention relates to integrated circuit (IC) chips and the clock signals used throughout the IC to drive, or xe2x80x9cclock,xe2x80x9d various active components on the IC. More particularly, the present invention relates to clock deskewing circuitry for minimizing undesirable skew, or offset, between coordinated clock signals for clocking related components of the IC.
Conventional integrated circuits (ICs) use a clock signal and branch it out through a series of buffers to form a plurality of clock signals. The structure of the branching of the clock signal is called a xe2x80x9cclock tree.xe2x80x9d One or more clock trees can be present in a single IC. For example, a clock signal at a given branch, or level, of the clock tree may feed into three buffers to produce three clock signals at the next level, which may each feed into three more buffers to produce nine clock signals at the third level. The clock signals at any level of the clock tree are sent to various synchronous components of the IC to coordinate the functions of these components. For various reasons, however, any two clock signals, even at the same level of the same clock tree, may be slightly different or offset from each other. This difference in clock signals is called xe2x80x9cclock skew,xe2x80x9d and differences throughout several clock signals of any level of the clock tree is called xe2x80x9cclock tree skew.xe2x80x9d
Clock tree skew has several causes. For example, the buffers between levels in the clock tree typically introduce a delay between their input and output clock signals, so clock signals at different levels of the clock tree are usually naturally skewed from each other. Additionally, the load experienced by one clock signal may introduce a delay into the clock signal different from that of another load on another clock signal. Furthermore, changes in temperature, different applied voltages and differing semiconductor fabrication processes can affect the clock skew.
Occasionally, the skew between two crock signals is introduced intentionally to precisely coordinate the operation of two components in the IC. Often, however, the skew must be reduced or eliminated for the IC to operate at a desired high operating clock frequency, where all or a portion of the synchronous components of the IC must switch states simultaneously or synchronously.
Common IC fabrication techniques try to minimize clock tree skew by resizing buffers in the clock tree to move some of the clock signals forward or backward or by adding redundant loads to the circuits to balance the loading of the clock tree. Either technique alters the delay of some of the clock signals by a specified amount that is determined by analysis of the timing of the clock signals. Such techniques typically result in a minimum clock skew of about 200 to 400 picoseconds after the clock trees have been placed, resized and routed through the IC chip. However, the 200 to 400 picosecond skew is usually a nominal target value that is still sometimes too large for high-speed operation of some ICs, such as many Application-Specific Integrated Circuits (ASICs). With temperature changes, different applied voltages, differing silicon fabrication processes and/or inadequate tolerances in the silicon fabrication processes, the clock skew can even vary significantly from the nominal value. Due to this variation in clock skew, such ICs will often fail speed testing and not meet performance targets. As a result, IC fabrication yields will be low and costs will be high.
It is with respect to these and other background considerations that the present invention has evolved.
The present invention enables dynamic self-detection and correction of clock tree skew in an integrated circuit (IC). Clock skew variations due to temperature changes, different applied voltages and different semiconductor fabrication processes are also corrected. Thus, as clock skew increases or decreases during operation of the IC, the present invention dynamically detects and corrects the changing clock skew on-the-fly. In this manner, the adjustment of each clock signal in a clock tree does not rely on a single determination and adjustment of the anticipated clock skew during the design of the IC, but is altered and re-altered as is dynamically determined to be appropriate by a skew detection and adjustment circuitry, particularly in response to differences in applied voltage, temperature and fabrication process.
In the skew detection and adjustment circuitry of the present invention, each clock signal in a clock tree is paired with another clock signal in the clock tree. The absolute skew between the two clock signals in each pair is detected, and one of the clock signals of each pair is adjusted forward or backward as appropriate. Such adjustment of one of the clock signals of the pair is performed by adding or subtracting a certain amount of delay from the adjusted clock signal. The detection and adjustment is repeated in increments as necessary to reach an acceptable minimum skew. Thus, the invention has the advantage of automatically correcting for almost any amount of clock skew. Additionally, since the skew detection and adjustment circuitry dynamically detects and corrects absolute skew between any two clock signals, the invention has the further advantage of automatically correcting for clock skew variations due to different applied voltages and/or different semiconductor fabrication processes that could not be anticipated during the design of the IC.
The detection and adjustment is also preferably performed during the operation of the IC to account for changing clock skew patterns. Thus, the invention has the additional advantage of continuing to operate at a high speed under changing conditions, such as changing ambient temperature.
These and other improvements are achieved in an IC comprising a clock tree, a plurality of synchronized circuit components and a clock tree deskew circuit. The clock tree includes a plurality of levels of clock signals, some of which operate the synchronized circuit components. Each clock signal has a delay characteristic relative to the other clock signals, which together define a clock tree skew. The clock tree deskew circuit is connected to the clock tree and the synchronized circuit components to intercept clock signals that are received by the synchronized circuit components. The clock tree deskew circuit determines the skew between pairs of the clock signals and changes the delay characteristic of one of the clock signals of at least one of the pairs to reduce the clock tree skew.
The clock tree deskew circuit preferably includes a plurality of skew adjust circuits and a corresponding plurality of skew detect circuits. The clock tree deskew circuit also preferably sends output clock signals to the synchronized circuit components. Each skew adjust circuit corresponds to and produces one of the output clock signals. The skew detect circuits connect to their corresponding skew adjust circuits to receive the corresponding output clock signal. Each skew detect circuit also receives one of the other output clock signals. Each skew detect circuit produces an adjustment signal to its corresponding skew adjust circuit indicative of whether the corresponding output clock signal preceded the other output clock signal. Each skew adjust circuit preferably receives the adjustment signal and shifts the corresponding output clock signal accordingly.
The clock tree deskew circuit preferably repeatedly determines the skew between the pairs of clock signals and repeatedly changes the delay characteristic of one of the clock signals of at least one of the pairs to minimize the clock tree skew over a period of time. After the period of time has elapsed, the clock tree deskew circuit preferably stops changing the delay characteristics of the clock signals. Then, when a condition of the IC changes that alters the delay characteristics of any of the clock signals, the clock tree deskew circuit preferably restarts the changing of the delay characteristics of the clock signals to minimize the clock tree skew again.
The previously mentioned and other improvements are also achieved in a method of controlling the skew between clock signals in an integrated circuit having a plurality of synchronized circuit components, The clock signals are generated in a plurality of levels of a clock tree. Each clock signal is paired with at least one other clock signal. The clock signal that precedes the other crock signal of each pair is detected. The timing is changed for one of the clock signals of at least one pair to reduce the skew between the clock signals of that pair. The skew between the clock signals is preferably minimized by repeating the adjustment over a period of time and then preferably discontinuing the adjustments. The adjustments are preferably restarted when conditions change in order to minimize the skew again.
These and other improvements are also achieved in a clock tree deskew circuit for deskewing clock signals of a clock tree that synchronize operation of synchronized circuit components in an IC. The clock tree deskew circuit comprises a plurality of clock signal inputs, a plurality of skew adjust circuits and a plurality of skew detect circuits. The clock signal inputs receive clock signals from the clock tree. The skew adjust circuits each buffer and delay a corresponding clock signal. Each skew detect circuit receives the corresponding buffered clock signal from a corresponding skew adjust circuit plus one other clock signal from one of the other skew adjust circuits. Each skew detect circuit determines whether the corresponding clock signal preceded or followed the other clock signal and issues an adjustment signal to the corresponding skew adjust circuit depending on which signal preceded the other. Each skew adjust circuit responds to the adjustment signal by adjusting the corresponding clock signal accordingly. The skew adjust circuits preferably minimize the clock tree skew by repeatedly adjusting the corresponding clock signals, while the skew detect circuits repeatedly determine which clock signal preceded the other and repeatedly issue the adjustment signals.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.